The state of the art is believed to be represented by the following publications inter alia:    [1] “Interleaving policies for flash memory”, United States Patent 20070168625    [2] “Minimization of FG-FG coupling in flash memory”, U.S. Pat. No. 6,996,004    [3] Construction of Rate (n−1)/n Punctured Convolutional Code with Minimum Required SNR Criterion, Pil J. Lee, IEEE Trans. On Comm. Vol. 36, NO. 10, October 1988    [4] “Introduction to Coding Theory”, Ron M. Roth, Cambridge University Press, 2006 5. U.S. Pat. Nos. 5,077,737; 6,781,910; 6,873,543; 6,891,768; 6,914,809; 6,961,890 to Smith; 6,990,012; 7,079,436; 7,149,950; and 7,191,379; Published US Applications 2004015771; 2005172179; 2007226592; and 2007171730; and Published PCT Application No. WO2006013529.    [5] Coded modulation to increase storage capacity of multilevel memories, Hui-Ling Lou; Sundberg, C.-E. Global Telecommunications Conference, 1998. GLOBECOM 98. The Bridge to Global Integration. IEEE Volume 6, Issue, 1998 Page(s):3379-3384 vol. 6    [6] On-chip error correcting techniques for new-generation flash memories, Gregori, S.; Cabrini, A.; Khouri, O.; Torelli, G., Proceedings of the IEEE, Volume 91, issue 4, April 2003 Page(s): 602-616    [7] Multi-level memory systems using error control codes, Hsie-Chia Chang; Chien-Ching Lin; Tien-Yuan Hsiao; Jieh-Tsorng Wu; Ta-Hui Wang, Circuits and Systems, 2004. ISCAS apos; 04. Proceedings of the 2004 International Symposium on Volume 2, Issue, 23-26 May 2004 Page(s): II-393-6 Vol. 2.    [8] Paulo Cappelletti, Clara Golla, Piero Olivo, Enrico Zanoni, “Flash Memories”, Kluwer Academic Publishers, 1999    [9] G. Campardo, R. Micheloni, D. Novosel, “CLSI-Design of Non-Volatile Memories”, Springer Berlin Heidelberg New York, 2005.
The disclosures of all publications and patent documents mentioned in the specification, and of the publications and patent documents cited therein directly or indirectly, are hereby incorporated by reference.